Course Description
Using the Quartus® II software version 15.0 and building upon your basic understanding of creating Synopsys Design Constraint (SDC) timing constraints, this class will guide you towards understanding, in more depth, timing exceptions. You will learn how to apply timing constraints to more advanced interfaces such as source synchronous single-data rate (SDR), double-data rate (DDR) and LVDS, as well as clock and data feedback systems. You will discover how to write timing constraints directly into an SDC file rather than using the GUI and then enhance the constraint file using TCL constructs. You will also perform timing analysis through the use of TCL scripts.
At Course Completion
You will be able to:
- Write Tcl script files to automate constraining and analysis of FPGA designs
- Apply timing exceptions to real design situations
- Properly constrain and analyze the following design situations: source synchronous interfaces, external feedback designs, and high-speed interfaces containing dedicated SERDES hardware
Skills Required
- Experience with PCs and the Windows operating system
- Completion of "The Quartus II Software Design Series: Timing Analysis" course OR a working knowledge of the TimeQuest timing analyzer and basic SDC commands
Prerequisites
We recommend completing the following courses:
- The Quartus Prime Software Design Series: Timing Analysis
- The Quartus Prime Software: Foundation (Instructor-led / Virtual Training)
- The Quartus Prime Software: Foundation (Standard Edition) (Online Training)
- TimeQuest Timing Analyzer: Introduction to Timing Analysis
Follow-on Courses
Upon completing this course, we recommend the following courses (in no particular order):
Related Courses
Below are the related courses you may be interested in:
Applicable Training Curriculum
This course is part of the following Altera training curriculum: