Advanced Verilog HDL Design Techniques

Course Description

You will learn efficient coding techniques for writing synthesizable Verilog for programmable logic devices (FPGAs and CPLDs). While the concepts presented mainly target Altera® FPGA devices using the Quartus® II software, many can be applied to other devices and synthesis tools as well. You will gain experience in behavioral and structural coding while learning how to effectively write common logic functions including registers, memory, and arithmetic functions. You will learn how to use Verilog constructs to parameterize your design, increasing their flexibility and reusability. You will be introduced to testbenches and Verilog constructs used when building them. The exercises will use the Quartus II software to synthesize Verilog code and the ModelSim®-Altera tool for simulation.

At Course Completion

You will be able to:

  • Implement synthesizable sequential and combinatorial RTL code
  • Design finite state machines using multiple encoding schemes
  • Develop simple testbenches for verification
  • Use tools in the Quartus II software to synthesize code and verify results
  • Run functional simulations in the ModelSim-Altera software

Skills Required

  • Completion of the "Introduction to Verilog HDL" course or some prior knowledge and use of Verilog hardware description language (HDL)
  • Background in digital logic design
  • Understanding of synthesis and simulation processes


We recommend completing the following courses:

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Altera training curriculum:


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