Course Description
Learn to design for a system containing the ARM® Cortex-A9 Hard Processor System (HPS) on Cyclone® V, Arria® V, & Arria 10 SoCs. This course focuses on the hardware aspects of designing the SoC system & includes hands-on labs to get you up & running quickly. Learn to add & configure the processor component into a Qsys system. You'll perform debug of the hardware system using standard debug tools such as SignalTap II logic analyzer & System Console. We'll discuss hardware to software files handoff that simplifies aspects of software development. You'll perform low-level debug of the FPGA interacting with the software debugger. We'll also discuss various ways the FPGA & HPS components can be loaded & booted. At completion, you'll be able to use the SoC device in your own design.
At Course Completion
You will be able to:
- Create, manage, and compile an SoC based FPGA in the Qsys tool
- Simulate the HPS interfaces using Qsys testbench and simulation model generation features
- Bring up and debug an SoC with the System Console tool
- Explain the hardware to software file handoff
- Design and debug with a Cyclone V based development kit
Skills Required
- FPGA knowledge is not required, but a plus
Prerequisites
We recommend completing the following courses:
- Advanced Qsys System Integration Tool Methodologies
- Introduction to the Qsys System Integration Tool
Follow-on Courses
Upon completing this course, we recommend the following courses (in no particular order):
Related Courses
Below are the related courses you may be interested in:
- SoC Hardware Overview: System Management, Debug, and General Purpose Peripherals
- SoC Hardware Overview: the Microprocessor Unit
Applicable Training Curriculum
This course is part of the following Altera training curriculum: