The Quartus Prime Software Design Series: Timing Analysis

Course Description

You will learn how to constrain and analyze a design for timing using the TimeQuest timing analyzer in the Quartus® software v. 16.0. This includes understanding FPGA timing parameters, writing Synopsys Design Constraint (SDC) files, generating various timing reports in the TimeQuest timing analyzer & applying this knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets timing, you will see how the TimeQuest timing analyzer makes it easy to create timing constraints to help you meet those requirements.

At Course Completion

You will be able to:

  • Understand the TimeQuest timing analyzer timing analysis design flow
  • Apply basic and complex timing constraints to an FPGA design
  • Analyze an FPGA design for timing using the TimeQuest timing analyzer
  • Write and manipulate SDC files for analysis and controlling the Quartus compilation

Skills Required

  • Experience with PCs and the Windows operating system
  • Completion of "The Quartus Prime Software Design Series: Foundation" online or instructor-led course OR a working knowledge of the Quartus software


We recommend completing the following courses:

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Related Courses

Below are the related courses you may be interested in:

Applicable Training Curriculum

This course is part of the following Altera training curriculum:


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